1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a DRAM (dynamic random access memory) type semiconductor memory device wherein each of dynamic memory cells is constructed to store a plurality of bit data.
2. Description of the Related Art
A semiconductor memory device of this kind, as disclosed in Japanese Laid-Open Patent Publication Hei 3-16094, structures each of memory cells to include two transistors and one capacitor to store two bit data.
Describing in more detail with reference to FIG. 10, each memory cell array comprises a plurality of memory cells 20. Each memory cell stores data for two bits with one capacitor. In the memory cell, reference numeral 21 denotes a storage capacitor; 22 and 23, transfer gates for reading out data stored in the storage capacitor 21 on bit lines; and 24 and 25, storage nodes. The reference numerals 26 and 27 denote sense amplifiers.
Referring to the input timing waveforms shown in FIG. 11, when bit line equalize control signals NEQ and PEQ change at time t0, all transistors in a bit line equalize circuit are turned off, whereby precharging for bit lines is completed and bit line voltages at all bit lines become equal to 1/2 Vcc.
Subsequently, when a memory cell 20 connected to a pair of bit lines BL1 and /BL2 (symbol "/" denotes a complementary signal) is selected, a signal CUT2 makes transistors of a cut off circuit of a sense amplifier turn off. Thus, a voltage at a word line WLL1 is raised up at time t1.
Upon being raised up of the word line WLL1, data stored in the storage capacitor 21 is transferred as charges to bit lines BLL1, BLR1, SBL1, SBL2, and /BLL1, /BLR1, /SBL1, /SBL2.
At time t2, when signals CUT1 and REQ are dropped, the bit line and the sense amplifier located at the memory cell side are separated from each other, whereby bit lines SBL1, SBL2 and /SBL1, /SBL2 are also separated from each other, respectively. Thus, the sense amplifiers 26 and 27 will individually hold the same data of the memory cell 20. At time t3, signals UP and DOWN are changed.
Thereafter, at time t4, the sense amplifier starts its sense amplifying operation upon receipt of a signal /SAS. At time t5, the signals CUT1 and CUT2 are raised up so that the sense amplifier and the bit line located at the memory cell side are connected to each other, thereby performing a pulling-up operation with a signal /SAS.
Finally, at time t6, a signal CSEL is dropped, whereby the amplified data in the memory cell is transferred to a data line. Thus, a reading operation is completed.
Since the conventional semiconductor memory device stores data for two bits at one storage capacitor, as is shown in Table 1, there are four states of voltages at the storage nodes 24 and 25 when data is being held in the memory cell. Data illustrated in Table 1 indicates information that is provided to data lines D1 and D2, and "H" corresponds to a voltage Vcc, "L", a voltage GND.
TABLE 1 ______________________________________ D1 = H, D1 = H, D1 = L, D1 = L, DATA D2 = H D2 = L D2 = H D2 = L ______________________________________ NODE 14 Vcc 2/3 Vcc 1/3 Vcc GND NODE 15 GND 1/3 Vcc 2/3 Vcc Vcc ______________________________________
In Table 1, FIG. 12 shows the waveforms at the bit lines SBL1 and SBL2 when the data are read out from the data lines D1 and D2 at a level "H". FIG. 13 shows the waveforms at the bit lines SBL1 and SBL2 when data are read out from the data line D1 at the level "H" and the data line D2 at a level "L".
In the case where the data is read out from the data lines D1 and D2 at the level "H", at time 1 when the voltage at the word line is raised up, a potential difference .DELTA.V occurs between the bit lines which are in a complementary relationship. At time t3, the signals UP and DOWN increase the voltages of the bit lines SBL1 and /SBL2 by 1/3 .DELTA.V. On the other hand, the signal UP and DOWN decreases the voltages of the bit lines /SBL and SBL2 by 1/3 .DELTA.V.
However, the voltages at bit lines SBL1 and /SBL1 are not reversed in level. The voltages at the bit lines SBL2 and /SBL2 are not also reversed in level. After the sense amplifier starts its amplifying operation at time t4, signals at the level Vcc are output from the data lines D1 and D2.
On the other hand, in the case where data are read out from the data line D1 at the level "H" and the data line D2 at the level "L", at time t1 when the voltage at the word line is raised up as shown in FIG. 13, the potential difference as little as 1/3 .DELTA.V occurs between the pair of the bit lines which are in the complementary relationship. Thus, at time t3, the voltages at the bit lines SBL1 and /SBL2 are increased by 1/3 .DELTA.V by the signals UP and DOWN. On the other hand, the voltages at the bit lines /SBL1 and SBL2 are reduced by 1/3 .DELTA.V. Thus, the voltages at the bit lines SBL2 and /SBL2 are reversed in level. Therefore, after the sense amplifier starts its amplifying operation at time t4, a signal at the level Vcc is output from the data line D1 and a signal at the level GND is output from the data line D2.
However, the foregoing semiconductor memory device has the memory cell array structure different from that of the conventional general DRAM, which has a memory cell consisting of one transistor and one capacitor. Therefore, a manufacturing method of the semiconductor memory device is also different.
Furthermore, two wirings must be drawn out from the both electrodes of the capacitor through the two transistors to the complementary bit lines, respectively. When it is intended to make the semiconductor memory device having such memory cell structure with a high integration, it is difficult to lay out elements symmetrically in the semiconductor memory device. This brings about a degrade of a margin such as a reading out margin.